As integrated circuit (“IC”) technologies are scaled to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing processes introduce uncertainties in circuit behavior, thereby significantly impacting the circuit performance and product yield. The problem is exacerbated by the increasing impact of environmental fluctuations, such as variations in temperature and voltage supply. Current design methodology needs a new paradigm to address the nano-scale manufacturing and design realities; specifically, how to consider large-scale variations at all levels of design hierarchy.
To consider large scale variations at all design hierarchy levels, various algorithms have been recently proposed for statistical timing analysis with consideration of large-scale variations. Current solutions fall into one of two broad categories: path-based approaches and block-based approaches. The path-based approaches can take into account the correlations from both path sharing and global parameters; however, the set of critical paths must be pre-selected based on their nominal delay values. See, for example, “Statistical timing analysis for intra-die process variations with spatial variations”, Agarwal et al, IEEE/ACM ICCAD, pp. 900-907, 2003). In contrast, the block-based statistical timing analysis is more general, yet is limited by the variation modeling assumptions. In particular, it has been demonstrated that since many circuit delays can be accurately approximated as Normal distributions, the spatial correlations and re-convergent fan outs can be handled efficiently for a block-based timing analysis. (See, for example, “Statistical timing analysis considering spatial correlations using a single PERT-like traversal”, H. Chang and S. Sapatnekar, IEEE/ACM ICCAD, pp. 621-625, 2003).
While these statistical timing analysis algorithms have been intensively studied, precisely how to interpret and utilize their results remains an open question. A critical need exists for a new methodology in the statistical domain for using timing analysis results to guide timing optimization, as well as to explore the tradeoff between performance, yield and cost.
In nominal timing analysis, critical path and slack are two important concepts that have been widely utilized for timing optimization, but the inclusion of large-scale process variations renders these concepts obsolete.
Firstly, the delay of each path is a random variable, instead of a deterministic value, in statistical timing analysis. As such, every path can be critical (i.e. have the maximal delay) with certain probability. Secondly, the slacks at all nodes are random variables that are statistically coupled. The overall timing performance is determined by the distributions of all these slacks, as well as their correlations. This implies that individual slack at a single node is not meaningful and cannot be utilized as a criterion to guide timing optimization. Therefore, the traditional critical path and slack definitions are no longer valid. What is needed is a method for optimizing timing in integrated circuits at or near the nano-scale where such a method accommodates that large scale process and environmental variations.